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These `-m' options are defined for Advanced RISC Machines (ARM)
Generate a stack frame that is compliant with the ARM Procedure Call
Standard for all functions, even if this is not strictly necessary for
correct execution of the code. Specifying `-fomit-frame-pointer'
with this option will cause the stack frames not to be generated for
leaf functions. The default is `-mno-apcs-frame'.
This is a synonym for `-mapcs-frame'.
Generate code for a processor running with a 26-bit program counter,
and conforming to the function calling standards for the APCS 26-bit
option. This option replaces the `-m2' and `-m3' options
of previous releases of the compiler.
Generate code for a processor running with a 32-bit program counter,
and conforming to the function calling standards for the APCS 32-bit
option. This option replaces the `-m6' option of previous releases
of the compiler.
Generate code to check the amount of stack space available upon entry to
every function (that actually uses some stack space). If there is
insufficient space available then either the function
`__rt_stkovf_split_small' or `__rt_stkovf_split_big' will be
called, depending upon the amount of stack space required. The run time
system is required to provide these functions. The default is
`-mno-apcs-stack-check', since this produces smaller code.
Pass floating point arguments using the float point registers. This is
one of the variants of the APCS. This option is reccommended if the
target hardware has a floating point unit or if a lot of floating point
arithmetic is going to be performed by the code. The default is
`-mno-apcs-float', since integer only code is slightly increased in
size if `-mapcs-float' is used.
Generate reentrant, position independent code. This is the equivalent
to specifying the `-fpic' option. The default is
Generate code which supports calling between the ARM and THUMB
instruction sets. Without this option the two instruction sets cannot
be reliably used inside one program. The default is
`-mno-thumb-interwork', since slightly larger code is generated
when `-mthumb-interwork' is specified.
Prevent the reordering of instructions in the function prolog, or the
merging of those instruction with the instructions in the function's
body. This means that all functions will start with a recognisable set
of instructions (or in fact one of a chioce from a small set of
different function prologues), and this information can be used to
locate the start if functions inside an executable piece of code. The
default is `-msched-prolog'.
Generate output containing floating point instructions. This is the
Generate output containing library calls for floating point.
Warning: the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
`-msoft-float' changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile `libgcc.a', the
library that comes with GNU CC, with `-msoft-float' in order for
this to work.
Generate code for a processor running in little-endian mode. This is
the default for all standard configurations.
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
This option only applies when generating code for big-endian processors.
Generate code for a little-endian word order but a big-endian byte
order. That is, a byte order of the form `32107654'. Note: this
option should only be used if you require compatibility with code for
big-endian ARM processors generated by versions of the compiler prior to
Do not try to load half-words (eg `short's) by loading a word from
an unaligned address. For some targets the MMU is configured to trap
unaligned loads; use this option to generate code that is safe in these
Use unaligned word loads to load half-words (eg `short's). This
option produces more efficient code, but the MMU is sometimes configured
to trap these instructions.
This is a synonym for the `-mno-short-load-bytes'.
This is a synonym for the `-mshort-load-bytes'.
This option only applies to RISC iX. Emulate the native BSD-mode
compiler. This is the default if `-ansi' is not specified.
This option only applies to RISC iX. Emulate the native X/Open-mode
This option only applies to RISC iX. Do not run the assembler
post-processor, `symrename', after code has been assembled.
Normally it is necessary to modify some of the standard symbols in
preparation for linking with the RISC iX C library; this option
suppresses this pass. The post-processor is never run when the
compiler is built for cross-compilation.
This specifies the name of the target ARM processor. GCC uses this name
to determine what kind of instructions it can use when generating
assembly code. Permissable names are: arm2, arm250, arm3, arm6, arm60,
arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi,
arm70, arm700, arm700i, arm710, arm710c, arm7100, arm7500, arm7500fe,
arm7tdmi, arm8, strongarm, strongarm110
This specifies the name of the target ARM architecture. GCC uses this
name to determine what kind of instructions it can use when generating
assembly code. This option can be used in conjunction with or instead
of the `-mcpu=' option. Permissable names are: armv2, armv2a,
armv3, armv3m, armv4, armv4t
This specifes the version of the floating point emulation available on
the target. Permissable values are 2 and 3.
The size of all structures and unions will be rounded up to a multiple
of the number of bits set by this option. Permissable values are 8 and
32. The default value varies for different toolchains. For the COFF
targeted toolchain the default value is 8. Specifying the larger number
can produced faster, more efficient code, but can also increase the size
of the program. The two values are potentially incompatible. Code
compiled with one value cannot necessarily expect to work with code or
libraries compiled with the other value, if they exchange information
using structures or unions. Programmers are encouraged to use the 32
value as future versions of the toolchain may default to this value.
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