ColdFire Reference Card

Release 1.0 (C) 1999 E&CE Department, University of Waterloo. All Rights Reserved.
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Mneumonic

Addressing modes

Bit Pattern

Condition
Codes

ADD (L)
add two values

Source + destination -> destination
ADD <ea>y + Dx --> Dx; ADD Dx + <ea>y --> <ea>y

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•	•	•	•	•			•	•

1101 Register[3] Opmode[3] EA-mode[3] EA-register[3]

Opmode:
010: <ea>y + Dx --> Dx
110: Dx + <ea>y --> <ea>y

X N Z V C

ADDA (L)
add address

Source + destination -> destination
ADDA <ea>y,Ax

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

1101 R[3] 111 EA-mode[3] EA-register[3]

not affected

ADDI (L)
add immediate

Immediate Data + destination -> destination
ADDI #<data>,Dx

0000 0110 1000 0 R[3]
upper word of immediate data[16]
lower word of immediate data[16]

X N Z V C

ADDQ (L)
add quick

Immediate Data + destination -> destination
ADDQ #<data>,<ea>x

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•			•	•

0101 DATA[3] 010 EA-mode[3] EA-register[3]

X N Z V C

ADDX (L)
add with extend

Source + destination + X -> destination
ADDX Dy,Dx

1101 Register Dx[3] 11 0000 Register Dy[3]

X N Z V C

AND (L)
logical AND

Source + destination -> destination
AND Dy,<ea>x; AND <ea>y,Dx

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•	•	•	•	•	•

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•	•	•	•	•			•	•

1100 Register[3] Opmode[3] EA-mode[3] EA-register[3]

Opmode:
110: AND Dy,<ea>x
010: AND <ea>y,Dx

N Z V=0 C=0

ANDI (L)
logical AND immediate

Immediate Data + destination -> destination
ADDI #<data>,Dx

0000 0010 1000 0 Register[3]

N Z V=0 C=0

ASL, ASR
arithmetic shift left and right

Destination shifted by count -> destination
ASd Dy, Dx; ASd #<data>,Dx
where d is direction: L or R

1110 count register[3] dr[1] 1 0 ir[1] 00 register[3]

count register: specifies shift count
dr: direction: 0 shift right, 1 shift left
ir: 0 immediate shift count, 1 register shift

X N Z V=0 C

Bcc (B,W)
branch conditionally

If condtion true, then PC + dn -> PC
Bcc <label>; where cc is a condition code from the condition code table

0110 condition[4] displacement[8]

0110 condition[4] 0000 0000
displacement[16]

not affected

BCHG (B,L)
test bit and change

1. (<bit number> of Destination) -> Z
2. (<bit number> of Destination) -> <bit number> of destination
BCHG Dy,<ea>x; BCHG #<data>,<ea>x

Destination (1 and 2)

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
L		•	•	•	•	•			•	•
L		•	•	•	•

1. 0000 Register[3] 101 EA-mode[3] EA-register[3]

2. 0000 1000 01 EA-mode[3] EA-register[3]
0000 0000 bit number[8]

BCLR (B,L)
test bit and clear

1. (<bit number> of Destination) -> Z
2. 0 -> <bit number> of destination
BCLR Dy,<ea>x; BCLR #<data>,<ea>x

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
L		•	•	•	•	•			•	•
L		•	•	•	•

1. 0000 Register[3] 110 EA-mode[3] EA-register[3]

2. 0000 1000 10 EA-mode[3] EA-register[3]
0000 0000 bit number[8]

BRA (B,W)
branch

PC + dn -> PC
BRA <label>

0110 0000 displacement[8]

0110 0000 0000 0000
displacement[16]

not affected

BSET (B,L)
test bit and set

1.TEST (<bit number> of Destination) -> Z
2. 1 -> <bit number> of destination
BSET Dy,<ea>x; BSET #<data>,<ea>x

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
L		•	•	•	•	•			•	•
L		•	•	•	•

1. 0000 Register[3] 111 EA-mode[3] EA-register[3]

2. 0000 1000 11 EA-mode[3] EA-register[3]
0000 0000 bit number[8]

BSR (B,W)
branch to subroutine

SP - 4 -> SP; Next PC -> (SP); PC + dn -> PC
BSR <label>

0110 0001 displacement[8]

0110 0001 0000 0000
displacement[16]

not affected

BTST (B,L)
test bit

1.(<bit number> of Destination) -> Z
BTST Dy,<ea>x; BTST #<data>,<ea>x

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
L		•	•	•	•	•			•	•
L		•	•	•	•

1. 0000 Register[3] 100 EA-mode[3] EA-register[3]

2. 0000 1000 00 EA-mode[3] EA-register[3]
0000 0000 bit number[8]

CLR (B,W,L)
clear

0 -> destination

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•			•	•

0100 0010 size[2] EA-mode[3] EA-register[3]

size: 00 byte, 01 word, 10 long

N=0 Z=1 V=0 C=0

CMP (L)
compare

Destination - source -> cc
CMP <ea>y, Dx

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

1011 Register[3] 010 EA-mode[3] EA-register[3]

N Z V C

CMPA (L)
compare address

Destination - Source -> cc
CMPA <ea>y,Ax

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

1011 Register[3] 111 EA-mode[3] EA-register[3]

N Z V C

CMPI (L)
compare immediate

Destination - immediate data -> cc
CMPI #<data>,Dx

0000 1100 1000 0 Register[3]
Upper word of immediate data[16]
Lower word of immediate data[16]

N Z V C

EOR (L)
logical XOR

Source XOR destination -> destination
EOR Dy,<ea>x

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•			•	•

1011 Register[3] 110 EA-mode[3] EA-register[3]

N Z V=0 C=0

EORI (L)
logical XOR immediate

Immediate data XOR destination -> destination
EORI #<data>,Dx

0000 1010 1000 0 Register[3]
Upper word of immediate data[16]
Lower word of immediate data[16]

N Z V=0 C=0

EXT, EXTB (W,L)
sign extend

Destination sign - extended -> destination
EXT.W Dx (extend byte to word)
EXT.L Dx (extend word to longword)
EXTB.L Dx (extend byte to longword)

0100 100 Opmode[3] 000 Register[3]

Opmode:
010: EXT.W Dx
011: EXT.L Dx
111: EXTB.L Dx

N Z V=0 C=0

JMP (unsized)
jump

Target address -> PC
JMP <ea>y

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•			•	•	•	•	•	•

0100 1110 11 EA-mode[3] EA-register[3]

not affected

JSR (unsized)
jump to subroutine

SP-4 -> SP; Next PC -> (SP); Target address -> PC

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•			•	•	•	•	•	•

0100 1110 10 EA-mode[3] EA-register[3]

not affected

LEA (L)
load effective address

Effective address -> destination
LEA <ea>y, Ax

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•			•	•	•	•	•	•

0100 Register[3] 111 EA-mode[3] EA-register[3]

not affected

LINK (W)
link and allocate

SP - 4 -> SP; Ax -> (SP); SP -> Ax; SP + d16 -> SP
LINK Ax,#<displacement>

0100 1110 0101 0 Register[3]

not affected

LSL, LSR (L)
logical shift left and right

Destination shifted by count -> destination
LSd Dy,Dx; LSD #<data>,Dx (where d is direction: L or R)

1111 count/register[3] dr[1] 10 ir[1] 01 register[3]

X N Z V=0 C

MOVE, MOVEA (B,W,L)
move

Source -> Destination
Move <ea>y,<ea>x; MOVEA <ea>y,Ax

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•			•	•

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

Restricted modes

Source addressing mode	Destination Addressing mode
Dy, Ay, (Ay), (Ay)+,-(Ay)	All possible
(d16,Ay), (d16,PC)	All except (d8,Ay,Xi), (xxx).W, (xxx).L
(d8,Ay,Xi), (d8,PC,Xi), (xxx).W, xxx.(L), #<xxx>	All except (d8,Ay,Xi), (d16,Ay), (xxx).W, (xxx).L

00 Size[2] Destination-Register[3] Destination-Mode[3] Source-Mode[3] Source-Register[3]

Size: 01 byte; 11 word; 10 long

N Z V=0 C=0

MOVE from CCR (W)
move from condition code register

CCR -> destination
MOVE CCR,Dx

0100 0010 1100 0 Register[3]

not affected

MOVE to CCR (W)
move to condition code register

Source -> CCR
MOVE Dy,CCR; MOVE #<data>,CCR

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•											•

0100 0100 11 EA-mode[3] EA-register[3]

X N Z V C

MOVEM (L)
move multiple registers

Registers -> destination or Source -> Registers
MOVEM <list>,<ea>x; MOVEM <ea>y,<list>

Register to Memory or Memory to Register

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•			•

0100 1 dr[1] 0011 EA-mode[3] EA-register[3]
registers to transfer/modify bit mask[16]

dr: 0 register to memory; 1 memory to register

not affected

MOVEQ (L)
move quick

Immediate data -> destination
MOVEQ #<data>,Dx

0111 Register[3] 0 Data[8]

Data is 8 bits, sign-extended to a long

N Z V=0 C=0

MULS (W,L)
signed multiply

Source x destination -> destination
1. MULS.L <ea>y,Dx (32 x 32 -> 32)
2. MULS.W <ea>y,Dx (16 x 16 -> 32)

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•	•	•	•	•	•
•		•	•	•	•

1. Word
1100 Register[3] 111 Ea-mode[3] EA-register[3]

2. Long
0100 1100 00 EA-mode[3] EA-register[3]
0 Register Dx[3] 1000 0000 0000

N Z V=0 C=0

MULU (W,L)
unsigned multiply

Source x destination -> destination
1. MULU.L <ea>y,Dx (32 x 32 -> 32)
2. MULU.W <ea>y,Dx (16 x 16 -> 32)

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•	•	•	•	•	•
•		•	•	•	•

1. Word
1100 Register[3] 011 Ea-mode[3] EA-register[3]

2. Long
0100 1100 00 EA-mode[3] EA-register[3]
0 Register Dx[3] 0000 0000 0000

N Z V=0 C=0

NEG (L)
negate

0 - destination -> destination
NEG Dx

0100 0100 1000 0 Register[3]

X N Z V C

NEGX (L)
negate with extend

0 - destination - X -> destination
NEGX Dx

0100 0000 1000 0 Register[3]

X N Z V C

NOP (unsized)
no operation

No operation
NOP

0100 1110 0111 0001 = $4E71

not affected

NOT (L)
logical complement

~ destination -> destination
NOT Dx

0100 0110 1000 0 Register[3]

N Z V=0 C=0

OR (L)
logical inclusive-OR

Source OR destination -> destination
OR Dy,<ea>x; OR <ea>y,Dy

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•		•	•	•	•	•	•	•	•	•	•

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•	•	•	•	•			•	•

1000 Register[3] Opmode[3] EA-mode[3] EA-register[3]

Opmode:
110: OR Dy,<ea>x
010: OR <ea>y,Dy

N Z V=0 C=0

ORI (L)
logical inclusive-OR immediate

Immediate data OR destination -> destination
ORI #<data>,Dx

0000 0000 1000 0 Register[3]
Upper word of immediate data[16]
Lower word of immediate data[16]

N Z V=0 C=0

PEA (L)
push effective address onto stack

SP - 4 -> SP; <ea>y -> (SP)
PEA <ea>y

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•			•	•	•	•	•	•

0100 1000 01 EA-mode[3] EA-register[3]

not affected

RTS (unsized)
return from subroutine

(SP) -> PC; SP + 4 -> SP
RTS

0100 1110 0111 0101 = $4E75

not affected

SUB (L)
subtract

Destination - source -> destination
SUB Dy,<ea>x; SUB <ea>y,DY

Source

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
		•	•	•	•	•			•	•

1001 Register[3] Opmode[3] EA-mode[3] EA-register[3]

Opmode:
010: SUB Dy,<ea>x
110: SUB <ea>y,DY

X N Z V C

SUBA (L)
subtract address

Destination - source -> destination
SUBA <ea>y,Ax

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

1001 Register[3] 111 EA-mode[3] EA-register[3]

not affected

SUBI (L)
subtract immediate

Destination - immediate data -> destination
SUBI #<data>,Dx

0000 0100 1000 0 Register[3]
Upper word of immediate data[16]
Lower word of immediate data[16]

X N Z V C

SUBQ (L)
subtract quick

Destination - immediate data -> destination
SUBQ #<data>,<ea>x

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•			•	•

0101 data[3] 110 EA-mode[3] EA-register[3]

X N Z V C

SUBX (L)
subtract with extend

Destination - source -> destination
SUBX Dy,Dx

1001 Dx[3] 1 1000 0 Dy[3]

X N Z V C

Scc (B)
set according to condition

If condition true then 1s -> destination
else 0s -> destination
Scc Dx (cc is condition code, see condition codes table)

0101 Condtion[3] 1100 0 Register[3]

not affected

SWAP (W)
swap register words

0100 1000 0100 0 Register[3]

N Z V=0 C=0

TRAP (unsized)
trap

TRAP #<vector>

0100 1110 0100 Vector[4]

not affected

TST (B,W,L)
test operand

Destination tested -> condition codes
TST <ea>y

Destination

Dn	An	(An)	(An)+	-(An)	(d16,An)	(d8,An,Xi)	(d16,PC)	(d8,PC,Xi)	(xxx).W	(xxx).L	#<xxx>
•	•	•	•	•	•	•	•	•	•	•	•

0100 1010 Size[2] EA-mode[3] EA-register[3]

N Z V=0 C=0

UNLK (unsized)
unlink

Ax -> SP; (SP) -> Ax; SP+4 -> SP
UNLK Ax

0100 1110 0101 1 Register[3]

not affected

Effective Addressing Modes

Addressing Modes	Syntax	Mode Field	Register Field
Data Register Direct	Dn	000	register number
Address Register Direct	An	001	register number
Address Register Indirect	(An)	010	register number
Postincrement Address Register Indirect	(An)+	011	register number
Predecrement Address Register Indirect	-(An)	100	register number
8-bit index displacement Address Register Indirect	(d8,An,Xi)	110	register number
Program counter indirect with displacement	(d16,PC)	111	010
Program counter indirect with index 8-bit displacement	(d8,PC,Xi)	111	011
Absolute Short	(xxx).W	111	000
Absolute Long	(xxx).L	111	001
Immediate	#<xxx>	111	100

Condition Codes Register

The CCR is the least significant byte of the status register (SR). Bits 4-0 are the condition code flags:

X: Extend condition code (bit 4)
N: Negative condition code (bit 3)
Z: Zero condition code (bit 2)
V: Overflow condition code (bit 1)
C: Carry condition code (bit 0)

Condition Codes Table

Mnemonic	Condition	Encoding	Test
T (BRA)	True	0000	1
F (BSR)	False	0001	0
HI	High	0010	C' * Z'
LS	Lower or Same	0011	C + Z
CC (HI)	Carry Clear	0100	C'
CS (LO)	Carry Set	0101	C
NE	Not Equal	0110	Z'
EQ	Equal	0111	Z
VC	Overflow Clear	1000	V'
VS	Overflow Set	1001	V
PL	Plus	1010	N'
MI	Minus	1011	N
GE	Greater or Equal	1100	N * V + N' * V'
LT	Less Than	1101	N * V' + N' * V
GT	Greater Than	1110	N * V * Z' + N' * V' * Z'
LE	Less or Equal	1111	Z + N * V' + N' * V
A prime, ' indicates the complement.
A plus, + indicates an or operation.
A star, * indicates an and operation.

ASCII Chart

    0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F
0  NUL SOH STX ETX EOT ENQ ACK BEL BS  HT  LF  VT  FF  CR  SO  SI
1  DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM  SUB ESC FS  GS  RS  US
2   SP  !   "   #   $   %   &   '   (   )   *   +   ,   -   .   /
3   0   1   2   3   4   5   6   7   8   9   :   ;   <   =   >   ?
4   @   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O
5   P   Q   R   S   T   U   V   W   X   Y   Z   [   \   ]   ^   _
6   `   a   b   c   d   e   f   g   h   i   j   k   l   m   n   o
7   p   q   r   s   t   u   v   w   x   y   z   {   |   }   ~ DEL

Notes

Supervisor (privileged) instructions not included in chart.
While we have tried to be accurate, there are no guarantees that this chart is completely correct. If you find an error, please send mail to Roger.

Developed and produced by Ashish Mishra, E&CE Dept., U of W, 1999.