;This code initializes the ColdFire 5206 SWT and Timer1.

;The timer1 exception routine resets the SWT

;if its time-out period is less than that of the 

;SWT's.  If not, the SWT causes an exception and 

;halts the processor.

;

;Current implementation works if timer reference 

; is 0x00ff

;

;MBAR=0x01000000 for the M5204AN evaluation board

;MBAR=0x10000000 for the M5206AN evaluation board

;MBAR	equ	0x01000000	;example equate statement

;or any old MBAR setting

MBAR	equ	0x10000000	;MBAR statement used



;Registers used or potentially used for SWT operation

SIMR	equ	MBAR+0x003	;SIM Configuration Register

ICR8	equ	MBAR+0x01b	;ICR8 = Interrupt Control Reg for SWT

IMR	equ	MBAR+0x036	;Interrupt Mask Register

IPR	equ	MBAR+0x03a	;Interrupt Pending Register

RSR	equ	MBAR+0x040	;Reset Status Register

SYPCR	equ	MBAR+0x041	;System Protection Control Register

SWIVR	equ	MBAR+0x042	;Software Watchdog Interrupt Vector Register

SWSR	equ	MBAR+0x043	;Software Watchdog Service Register



;Timer1 registers

TMR1	equ	MBAR+0x100	;Timer Mode Register

TRR1	equ	MBAR+0x104	;Timer Reference Register

TCR1	equ	MBAR+0x108	;Timer Capture Register

TCN1	equ	MBAR+0x10c	;Timer Counter

TER1	equ	MBAR+0x111	;Timer Event Register



	XDEF	_main

_main:	

	nop

	nop

	nop

	nop

	move.l	#MBAR+1,d0	;the +1 sets the V-bit.

	movec.l	d0,MBAR



	clr.l	d6		;clear a register to increment 

				;inside the timer1 exception handler

				

	jsr	_init_timer1	;init timer1, but do not start it



	move.l	#1,-(a7)	;divide by 1,(ie: 8(a7))

	move.l	#1,-(a7)	;divide by 1, (ie: 4(a7))

	jsr	_start_timer1	;start timer1

	lea.l	8(a7),a7	;re-adjust stack



	jsr	_init_swt	;init SWT, and start it



	move.w	#0xFCFF,d0	;allow SWT and TIMER1 interrupts

	move.w	d0,IMR		;make it so



	move.w	#0x2000,d0	;lower IPL to zero

	move.w	d0,sr		;enable interrupts



;infintie loop waits for timer interrupt or SWT to occur

loop:	

	nop

	nop

	nop

	nop

	bra loop



	rts



;initialize the software watchdog (SWT)

	XDEF _init_swt

_init_swt:

	lea.l	_swt_exception_handler,a0	;used in exception table

	move.l	a0,0x100	;set handler to user defined interrupt #1

	move.l	#0x40,d0	;point SWIVR to user defined interrupt #1

	move.b	d0,SWIVR	;make it so...

	move.l	#0x1e,d0	;none AVEC,IL=7,IP=2

				;(Note: SWT is ALWAYS IL=7, IP can be whatever)

	move.b	d0,ICR8		;make it so...

	move.l	#0xa0,d0	;clear RSR HRST/SWTR bits

	move.b	d0,RSR		;make it so...

	move.l	#0x80,d0	;enable SWT, divide sys_clk/1(prescale=1),

				;cause interrupt every 1024 sys_clks

	move.b	d0,SYPCR	;make it so...

	rts





;TIMER1_ref is a global variable used to change the TIMER1 interrupt period

	TIMER1_ref:     dc.l    0x000000ff



;TIMER1 initialization routine

	XDEF	_init_timer1

_init_timer1:

	nop

	lea.l	_timer1_exception_handler,a0

	move.l	a0,0x0078.w	;load the timer1 exception handeler address

	move.w	#0x0038,d0	;TMR1 mask,toggle output, enable int,

				;reset cnt when tmr=0,timer stopped

	move.w	d0,TMR1



        move.l  TIMER1_ref,d0   ;initial reference value.

	move.w	d0,TRR1



	move.b	#0x98,d0	;mask for AVEC enabled, IL=6, IP=0

	move.b	d0,MBAR+0x1c	;write to ICR_T1



	move.l	#0x151e,d0	;mask to enable TIMER1 interrupt

	move.l	d0,MBAR+0x34	;write to IMR

	rts



;Start TIMER1 subroutine

_start_timer1:

	nop

	move.l	8(a7),d0	;divide by 1_to_256

	subq.l	#1,d0		;scale to 0-255

	lsl.l	#8,d0		;shift left 8 bits (MSB of TMR word)

	move.w	TMR1,d2		;get current TMR1 value

	and.l	#0x00ff,d2	;mask off MSB

	or.l	d0,d2		;put PS[7:0] into TMR1

	move.l	#1,d0		;used to set the ICLK[1:0] mask

	move.l	4(a7),d1	;divide internal clk by 1_or_16

	subq.l	#1,d1

	bne	div_by_16

	lsl.l	#1,d0		;ICLK[1:0]=01, divide internal clk by 1

	bra	div_by_1

div_by_16:

	lsl.l	#2,d0		;ICLK[1:0]=10, divide internal clk by 16

div_by_1:

	and.l	#~0x7,d2	;mask off lower three bits of current TMR1 value

	or.l	d0,d2		;put ICLK[1:0] into TMR1 

	bset	#0,d2		;enable timer1 in TMR1

	move.w	d2,TMR1		;write to register

	rts



	

;TIMER1 exception handler

	XDEF _timer1_exception_handler

_timer1_exception_handler:

	nop

	addq.l	#1,d6		;increment a counter to verify entrance into exception

	move.b	#2,d0

	move.b	d0,TER1		;clear the REF bit of TER by writing 1 to it.

	

	move.b	#0x55,d0	;

	move.b	d0,SWSR		;sequence to reset SWT

	move.b	#0xAA,d0	;

	move.b	d0,SWSR		; 

 	rte	



;SWT exception handler

	XDEF _swt_exception_handler

_swt_exception_handler:

	nop

	halt		;executing this halt to indicate that SWT works

	nop

	rte		;exit exception handler if halt commented out