Here is a table of the instruction names that are meaningful in the RTL generation pass of the compiler. Giving one of these names to an instruction pattern tells the RTL generation pass that it can use the pattern in to accomplish a certain task.
subregwith mode m of a register whose own mode is wider than m, the effect of this instruction is to store the specified value in the part of the register that corresponds to mode m. The effect on the rest of the register is undefined. This class of patterns is special in several ways. First of all, each of these names must be defined, because there is no other way to copy a datum from one place to another. Second, these patterns are not used solely in the RTL generation pass. Even the reload pass can generate move insns to copy values from stack slots into temporary registers. When it does so, one of the operands is a hard register and the other is an operand that can need to be reloaded into a register. Therefore, when given such a pair of operands, the pattern must generate RTL which needs no reloading and needs no temporary registers--no registers other than the operands. For example, if you support the pattern with a
define_expand, then in such a case the
force_regor any other such function which might generate new pseudo registers. This requirement exists even for subword modes on a RISC machine where fetching those modes from memory normally requires several insns and some temporary registers. Look in `spur.md' to see how the requirement can be satisfied. During reload a memory reference with an invalid address may be passed as an operand. Such an address will be replaced with a valid address later in the reload pass. In this case, nothing may be done with the address except to use it as it stands. If it is copied, it will not be replaced with a valid address. No attempt should be made to make such an address into a valid address and no routine (such as
change_address) that will do so may be called. Note that
general_operandwill fail when applied to such an address. The global variable
reload_in_progress(which must be explicitly declared if required) can be used to determine whether such special handling is required. The variety of operands that have reloads depends on the rest of the machine description, but typically on a RISC machine these can only be pseudo registers that did not get hard registers, while on other machines explicit memory references will get optional reloads. If a scratch register is required to move an object to or from memory, it can be allocated using
gen_reg_rtxprior to reload. But this is impossible during and after reload. If there are cases needing scratch registers after reload, you must define
SECONDARY_INPUT_RELOAD_CLASSand perhaps also
SECONDARY_OUTPUT_RELOAD_CLASSto detect them, and provide patterns `reload_inm' or `reload_outm' to handle them. See section Register Classes. The constraints on a `movem' must permit moving any hard register to any other hard register provided that
HARD_REGNO_MODE_OKpermits mode m in both registers and
REGISTER_MOVE_COSTapplied to their classes returns a value of 2. It is obligatory to support floating point `movem' instructions into and out of any registers that can hold fixed point values, because unions and structures (which have modes
DImode) can be in those registers and they may have floating point members. There may also be a need to support fixed point `movem' instructions in and out of floating point registers. Unfortunately, I have forgotten why this was so, and I don't know whether it is still true. If
HARD_REGNO_MODE_OKrejects fixed point values in floating point registers, then the constraints of the fixed point `movem' instructions must be designed to avoid ever trying to reload into a floating point register.
SECONDARY_RELOAD_CLASSmacro in see section Register Classes.
subregwith mode m of a register whose natural mode is wider, the `movstrictm' instruction is guaranteed not to alter any of the register except the part which belongs to mode m.
define_expand(see section Defining RTL Sequences for Code Generation) and make the pattern fail if the restrictions are not met. Write the generated insn as a
parallelwith elements being a
setof one register from the appropriate memory location (you may also need
clobberelements). Use a
match_parallel(see section RTL Template) to recognize the insn. See `a29k.md' and `rs6000.md' for examples of the use of this insn pattern.
HImode, and store a
SImodeproduct in operand 0.
find_reg_noteand look for a
REG_UNUSEDnote on the quotient or remainder and generate the appropriate instruction.
sqrtbuilt-in function of C always uses the mode which corresponds to the C data type
ffsbuilt-in function of C always uses the mode which corresponds to the C data type
(set (cc0) (compare (match_operand:m 0 ...) (match_operand:m 1 ...)))
(set (cc0) (match_operand:m 0 ...))`tstm' patterns should not be defined for machines that do not use
(cc0). Doing so would confuse the optimizer since it would no longer be clear which
setoperations were comparisons. The `cmpm' patterns should be used instead.
Pmode. The number of bytes to move is the third operand, in mode m. The fourth operand is the known shared alignment of the source and destination, in the form of a
const_intrtx. Thus, if the compiler knows that both source and destination are word-aligned, it may provide the value 4 for this operand. These patterns need not give special consideration to the possibility that the source and destination strings might overlap.
Pmode. The number of bytes to clear is the second operand, in mode m. The third operand is the known alignment of the destination, in the form of a
const_intrtx. Thus, if the compiler knows that the destination is word-aligned, it may provide the value 4 for this operand.
memreferring to the first character of the string, operand 2 is the character to search for (normally zero), and operand 3 is a constant describing the known alignment of the beginning of the string.
word_mode. Operand 1 may have mode
word_modeis allowed only for registers. Operands 2 and 3 must be valid for
word_mode. The RTL generation pass generates this instruction only with constants for operands 2 and 3. The bit-field value is sign-extended to a full word integer before it is stored in operand 0.
word_mode) into a bit field in operand 0, where operand 1 specifies the width in bits and operand 2 the starting bit. Operand 0 may have mode
word_modeis allowed only for registers. Operands 1 and 2 must be valid for
word_mode. The RTL generation pass generates this instruction only with constants for operands 1 and 2.
leu. You specify the mode that the operand must have when you write the
match_operandexpression. The compiler automatically sees which mode you have used and supplies an operand of that mode. The value stored for a true condition must have 1 as its low bit, or else must be negative. Otherwise the instruction is not suitable and you should omit it from the machine description. You describe to the compiler exactly which value is stored by defining the macro
STORE_FLAG_VALUE(see section Miscellaneous Parameters). If a description cannot be found that can be used for all the `scond' patterns, you should omit those operations from the machine description. These operations may fail, but should do so only in relatively uncommon cases; if they would fail for common cases involving integer comparisons, it is best to omit these patterns. If these operations are omitted, the compiler will usually generate code that copies the constant one to the target and branches around an assignment of zero to the target. If this code is more efficient than the potential instructions used for the `scond' pattern followed by those required to convert the result into a 1 or a zero in
SImode, you should omit the `scond' operations from the machine description.
label_refthat refers to the label to jump to. Jump if the condition codes meet condition cond. Some machines do not follow the model assumed here where a comparison instruction is followed by a conditional branch instruction. In that case, the `cmpm' (and `tstm') patterns should simply store the operands away and generate all the required insns in a
define_expand(see section Defining RTL Sequences for Code Generation) for the conditional branch operations. All calls to expand `bcond' patterns are immediately preceded by calls to expand either a `cmpm' pattern or a `tstm' pattern. Machines that use a pseudo register for the condition code value, or where the mode used for the comparison depends on the condition being tested, should also use the above mechanism. See section Defining Jump Instruction Patterns The above discussion also applies to the `movmodecc' and `scond' patterns.
SImode, except it is normally a
const_int); operand 2 is the number of registers used as operands. On most machines, operand 2 is not actually stored into the RTL pattern. It is supplied for the sake of some RISC machines which need to put this information into the assembler code; they can put it in the RTL instead of operand 1. Operand 0 should be a
memRTX whose address is the address of the function. Note, however, that this address can be a
symbol_refexpression even if it would not be a legitimate memory address on the target machine. If it is also not a valid argument for a call instruction, the pattern for this operation should be a
define_expand(see section Defining RTL Sequences for Code Generation) that places the address into a register and uses that register in the call instruction.
BLKmodeobjects use the `call' insn.
RETURN_POPS_ARGSis non-zero. They should emit a
parallelthat contains both the function call and a
setto indicate the adjustment made to the frame pointer. For machines where
RETURN_POPS_ARGScan be non-zero, the use of these patterns increases the number of functions for which the frame pointer can be eliminated, if desired.
parallelexpression where each element is a
setexpression that indicates the saving of a function return value into the result block. This instruction pattern should be defined to support
__builtin_applyon machines where special instructions are needed to call a subroutine with arbitrary arguments or to save the value returned. This instruction pattern is required on machines that have multiple registers that can hold a return value (i.e.
FUNCTION_VALUE_REGNO_Pis true for more than one register).
reload_completedis non-zero and the function's epilogue would only be a single instruction. For machines with register windows, the routine
leaf_function_pmay be used to determine if a register window push is required. Machines that have conditional return instructions should define patterns such as
(define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(cc0) (const_int 0)]) (return) (pc)))] "condition" "...")where condition would normally be the same condition specified on the named `return' pattern.
__builtin_returnon machines where special instructions are needed to return a value of any type. Operand 0 is a memory location where the result of calling a function with
__builtin_applyis stored; operand 1 is a
parallelexpression where each element is a
setexpression that indicates the restoring of a function return value from the result block.
(const_int 0)will do as an RTL pattern.
CASE_DROPS_THROUGHis defined, then an out-of-bounds index drops through to the code following the jump table instead of jumping to this label. In that case, this label is not actually used by the `casesi' instruction, but it is always provided as an operand.)
addr_diff_vecinside of a
jump_insn. The number of elements in the table is one plus the difference between the upper bound and the lower bound.
CASE_VECTOR_PC_RELATIVEis defined then the first operand is an offset which counts from the address of the table; otherwise, it is an absolute address to jump to. In either case, the first operand has mode
Pmode. The `tablejump' insn is always the last insn before the jump table it uses. Its assembler code normally has no need to use the second operand, but you should incorporate it in the RTL pattern so that the jump optimizer will not delete the table as unreachable code.
regand has mode
Pmode; operand 1 may be a
const_int, etc and also has mode
Pmode. Canonicalization of a function pointer usually involves computing the address of the function which would be called if the function pointer were used in an indirect call. Only define this pattern if function pointers on the target machine can have different values but still call the same function when used in an indirect call.
Pmode. Do not define these patterns on such machines. Some machines require special handling for stack pointer saves and restores. On those machines, define the patterns corresponding to the non-standard cases by using a
define_expand(see section Defining RTL Sequences for Code Generation) that produces the required insns. The three types of saves and restores are:
alloca. Only the epilogue uses the restored stack pointer, allowing a simpler save or restore sequence on some machines.
VOIDmodeif no save area is needed for a particular type of save (either because no save is needed or because a machine-specific save area can be used). Operand 0 is the stack pointer and operand 1 is the save area for restore operations. If `save_stack_block' is defined, operand 0 must not be
VOIDmodesince these saves can be arbitrarily nested. A save area is a
memthat is at a constant offset from
virtual_stack_vars_rtxwhen the stack pointer is saved for use by nonlocal gotos and a
regin the other two cases.
STACK_GROWS_DOWNWARDis undefined) operand 0 from the stack pointer to create space for dynamically allocated data. Do not define this pattern if all that must be done is the subtraction. Some machines require other operations such as stack probes or maintaining the back chain. Define this pattern to emit those operations in addition to updating the stack pointer.
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